1. Field of the Invention
The present invention relates to an apparatus which detects on/off status of switches arranged in a matrix style at respective intersections of input signal lines and output signal lines.
2. Description of the Related Art
In various types of electronic equipment for detecting operations of a plurality of key switches, it is desired to minimize the number of total signal lines that are connected to such key switches for the purpose of miniaturizing the equipment and simplifying key operation detection.
To this end a conventional system called a key matrix system is known in which a plurality of keys are arranged in a matrix at respective intersections of signal input and output lines such that the signal output lines form common inputs to all switches and the signal input lines provide common or time division multiplexed (TDM) outputs from all switches.
FIG. 1 shows a first prior art arrangement of the key matrix system in which a 3.times.3 array of key switches 1#(1) to 1#(9) are connected to form a key matrix circuit. Output terminals KO1 to KO3 of CPU7 are connected to respective inverters 3(#1) to 3(#3), which also functions as drivers. The inverters (drivers) 3(#1) to 3(#3) are connected to output signal lines l1 to l3 respectively. Three input signal lines ml to m3 cross each of the output signal lines. At three intersections of the first output signal line l1 and the input signal lines m1 to m3, there are formed diodes 2(#1), 2(#4) and 2(#7) with their anodes being coupled to the output signal line l1. Cathode sides of the diodes are connected to first terminals of key switches 1(#1), 1(#4) and 1(#7) respectively. Second terminals of the key switches 1(#1), 1(#4) and 1(#7) are connected to the input signal lines m1 to m3 respectively. Similarly, three intersections of the second output signal line l2 and the input signal lines m1 to m3 are formed by diodes 2(#2), 2(#5) and 2(#8) with their anodes coupled to the second output signal line, and with their cathodes respectively connected to first terminals of key switches 1(#2), 1(#5) and 1(#8). Second terminals of the key switches 1(#2), 1(#5) and 1(#8) are connected to the input signal lines m1 to m3 respectively. Similarly, at three intersections of the third output signal line l3 and the input signal lines m1 to m3, the output signal lines l3 is connected to each anode side of diodes 2(#3), 2(#6) and 2(#9). Cathode sides of the diodes 2(#3), 2(#6) and 2(#9) are connected to first terminals of key switches 1(#3), 1(#6) and 1(#9) respectively. Second terminals of the key switches 1(#3), 1(#6) and 1(#9) are connected to the-input signal lines m1 to m3 respectively.
The input signal lines m1 to m3 are connected to inverters 4(#1) to 4(#3) which also function as recliners. Each output of the inverters (receivers) is supplied to respective input terminals KI1 to KI3 of CPU7. Each inverter (receiver) 4(#1) to 4(#3) outputs a high level ("1") voltage when voltage of the input signal lines m1 to m3 is below a threshold level V.sub.TH, and is switched to a low level ("0") voltage when the voltage of the input signal lines exceeds the threshold level V.sub.TH.
There are shown capacitors 6(#1) to 6(#3) which couple the respective signal input lines m1 to m3 to ground. The line-ground capacitors 6(#1) to 6(#3) represent the respective capacitance of the input signal lines and also capacitors which may be actually inserted for noise elimination.
Resistors 5(#1) to 5(#3) termed pull-down resistors all have the same resistance R.sub.1 and are arranged to couple respective input signal lines to ground in parallel to the respective capacitors 6(#1) to 6(#3).
CPU7 outputs patterned control voltage signals (to be described later) to output terminals (ports) KO1 to KO3, and detects status, of key switches 1(#1) to (#9) from voltages which appear terminals KI1 to KI3.
An equivalent circuit of each key switch 1(#1) to 1(#9) in FIG. 1 is shown in FIGS. 3A and 3B. FIG. 3A shows an ideal one. In fact, however, there is a line resistance r including a contact resistance of the switch between terminals A and B, as shown in FIG. 3B. The value of the resistance r depends on the type of the key switch, used and an inexpensive key switch typically has a relatively large value of contact resistance.
In some applications, the output signal lines l1 to l3 and input signal lines m1 to m3 arranged on a print circuit board (not shown in FIG. 1) may have a large resistance of their own. Therefore, resistance r shown in FIG. 3B includes such resistances also.
FIGS. 2A to 2J show a time chart of operations of the first prior art arrangement in FIG. 1. Under the control of CPU7, the output terminals KO1 to KO3 supply voltage pulses as shown in FIGS. 2A to 2C in such a manner that the terminals KO1 to KO3 are set to a low level successively and cyclically.
READ pulses shown in FIG. 2D represent times at which CUP7 reads input signals which appear input on terminals KI1 to KI3. Each READ pulse occurs at a predetermined time T after a low-going edge of the outputs KO1 to, KO3 so that CPU7, reads switches 2(#1), 2(#4) and 2(#7) with KO1="low", reads switches 2(#2), 2(#5) and 2(#8) with KO2="low" and reads switches 2(#3), 2(#6) and 2(#9) with KO3="low" by receiving TDM input voltages which appear on KI1 to KI3 at respective READ pulse times.
Let us discuss a case where only the key switch 1(#1) is ON-actuated.
FIG. 4 shows an equivalent circuit involving the on-state key switch 1(#1) with KO1="Low" in which R.sub.0 denotes an "on" output impedance of (a pull-up transistor, not shown, of) the (driver) inverter 3(#1), V.sub.DD denotes a power source (positive) voltage coupled to the inverter (driver) 3(#1), r represents an on-resistance of key switch 1(#1) (refer to FIG. 3B), and R.sub.1 corresponds to a value of the pull-down resistor 5(#1) in FIG. 1. The receiver inverter 4(#1) is assumed to have a sufficiently large input impedance.
With the switch 1(#1)="ON", and KO1="LOW", an input voltage to the receiver inverter 4(#1) is obtained by dividing V.sub.DD less V.sub.F (forward bias of the diode 2(#1) by a factor determined by the voltage dividing circuit of R.sub.0, r and R.sub.1. Namely, the receiver input voltage is given by ##EQU1##
FIGS. 2E to 2G show inputs to receiver inverter 4(#1), and FIGS. 2H to 2J show inputs to a terminal KI1 of CPU7. Of these figures, FIGS. 2E and 2H represent a case 1 where a ratio of R.sub.0 +r to R.sub.1 appeared in equation (1) is correctly set, FIGS. 2F and 2I represent a case 2 when R.sub.1 is relatively too large, and FIGS. 2G and 2J represent a case 3 when R.sub.1 is too small.
More specifically, during the low level output KO1 period, in both cases of 1 and 2, an input voltage to the receiver inverter 4(#1) is sufficiently larger than the threshold voltage V.sub.TH as shown in FIGS. 2E and 2F so that the input voltage of the terminal KI1 assumes a correct level, indicative of "on-state" of the switch 1(#1) as shown in FIGS. 2H and 2I. On the contrary, in case 3 that uses a too small pull-down resistor R.sub.1, an input voltage of the inverter 4(#1) is erroneously below the threshold voltage V.sub.TH as shown in FIG. 2G so that a high level input voltage appears on the input terminal KI1 and faultly indicates "off-state" of the key switch 1(#1) though that switch is in fact operated. Therefore, there is a lower limit to the pull-down resistance R.sub.1 relative to the switch and driver resistances r and R.sub.0 for reliable detection of "on-state" of key switches.
The worst situation occurs when a plurality of key switches 1(#1), 1(#4) and 1(#7) are simultaneously actuated ON. FIG. 5 shows a relationship of resistances in the worst case with KO1="LOW". Note that, impedances of inverters 4(#2) and 4(#3) are not shown because those are sufficiently large and their effect could be negligible. In this figure, R.sub.0 denotes an ON-resistance of the driver inverter 3(#1), r's denote on-resistances of respective key switches 1(#1), 1(#4) and 1(#7), and three R.sub.1 's represent resistances of respective pull-down resistors 5(#1) to 5(#3). In FIG. 5, a current flowing through driver resistor R.sub.0 is three times the current flowing through respective pull-down resistors R.sub.1 's.
Therefore, an input voltage of the receiver inverter 4(#1) assumes ##EQU2## As noted, influence of the driver on-impedance R.sub.0 on the receiver input will become larger as a number of input signal lines increases. In general, for a number of the input signal lines n, the influence will be on the order of n.times.R.sub.0 in the case where all n key switches are actuated ON at the same time. Therefore, it is desired to use driver inverters 3(#1), 3(#2) and 3(#3) with a smaller value of on-impedance R.sub.0 for reliable detection of simultaneous on-operations of a plurality of key switches.
However, from a manufacturing point there is a lower limit to the value R.sub.0 because this is an on-resistance of a driver inverter that is one form of semiconductor device and typically fabricated as a CMOS inverter circuit, which may be formed in a large scaled integrated circuit (LSI) chip, generally accompanied by relatively high on-impedances. To compensate for this, the pull-down resistors can be made with a higher resistance R.sub.1 relative to the driver resistance, but this involves another problem discussed below.
In FIGS. 2A to 2J, such a problematic situation occurs during the low level output KO2 period (FIG. 2B) with respect to the off-state key switch 1#(2) that is to be read next after reading the on-state key switch 1#(1). In order to correctly detect the off-state of the key switch 1(#2), an input voltage to the receiver inverter 4(#1) must be lowered below the threshold level VTH (FIG. 2E) at READ pulse time (FIG. 2D) during the low KO2 period. However, in case 2, involving a relatively high value of the pull-down resistor 5(#1), an input level to the receiver inverter 4(#1) is still larger than V.sub.TH as shown in FIG. 2F at the time of READ pulse so that a low level input voltage is provided to the CPU terminal KI1, causing CPU7 to misread that the key switch 1(#2) is also actuated ON.
This is due to an electric charge stored in capacitor 6(#1) shown in FIG. 1 having failed to discharge to a desired extent through the pull-down resistor during a setting or waiting time T, because the pull-down resistor value R.sub.1 is too large.
The above-mentioned problem could be solved by making longer a period of time in which output voltages of KO1 to KO3 shown in FIGS. 2A to 2C are successively lowered and by lengthening a waiting time T to the READ pulse shown in FIG. 2D. However, if this is done then, one complete cycle Ts of detecting all key operations must also be longer, resulting in a slow response to key operations. Further, in a system which alternately executes a key operation detection (key scanning) with other processes, the speed of other processes is slowed down because of the time required for key scanning.
Especially, in a touch response featured electronic keyboard instrument that detects a key operation velocity by measuring an operation time difference between on-timings of two switches provided for each play key, it is important to provide an accurate time difference of switch-ON operations. If the above-mentioned prior art is applied to such an electronic keyboard instrument, this results in an undesirable system with slow and inaccurate touch response because of a considerable delay in detecting key operations.
Therefore, there is an upper limit to the value of the pull-down resistance R.sub.1 in order to minimize the time required for detecting key operations. This does restrict a number of output signal lines in the key matrix circuit. Further, a number of input signal lines are also limited because of an increased adverse effect of the driver inverter on-impedance R.sub.0 for simultaneous on-operations of an increased number of key switches, as discussed in conjunction with FIG. 5. For a given number of n.times.n key switches, a minimum and optimum number of signal lines are 2n, using n lines as input signal lines and also using n lines as output signal lines. However, if the number of n exceeds the limits of the prior art, there would be no other way but to subdivide the key switches into a plurality of, say, two groups such that a first group of key switches are connected to form a first key matrix circuit and a second group of key switches are connected to form a second and separate key matrix circuit. The first key matrix circuit is scanned by a first CPU or a key scanner hardware while the second key matrix circuit is scanned by a second CPU or a second key scanner hardware. The first and second key scanners provide key information to a (host) CPU. Such an arrangement, however, clearly adds complexity with an increased number of signal lines, separate key scanners, and complicated control of the entire system.
Next, a second prior art arrangement will be taken up.
This second prior art is constructed as shown in FIG. 6. As will be understood by comparing FIG. 6 with FIG. 1, the second prior art arrangement is operated in an opposite logic contrary to the first prior art arrangement.
More specifically, in the first prior art arrangement (refer to FIG. 1) CPU7 supplies output terminals KO1-KO3 with active "low" level pulses successively and cyclically in the order of KO1, KO2, KO3, KO1 and so on, and receives voltage levels on input terminals KI1-KI3 each time when a waiting time T has passed from the beginning of each low voltage pulse output. CPU7 then detects an ON-status of of any key switches 1(#1) to 1(#9) from a "low" level voltage of KI1 to KI3. These operations are already described by referring to time charts shown in FIGS. 2A to 2J.
On the contrary, in the second prior art (refer to FIG. 6) CPU7, outputs "high" level pulses to and in the order of KO1, KO2, KO3, KO1 and so on as shown in FIGS. 7A to 7C. Further, similarly to the first prior art, arrangement CPU7 arrangement receives voltages which appear on the input terminals KI1 to KI3 each time when a settling time T has passed from the beginning of the high voltage pulse output as shown in FIG. 7D, and detects an ON-status of any of key switches 1(#1) to 1(#9) when a corresponding voltage level of KI1 to KI3 is "high".
The second prior art arrangement has the same problem as the first prior art arrangement.
Let us consider again an example in which only the key switch 1(#1) is actuated ON.
In this condition, there is formed an equivalent circuit associated with the on-state key switch 1(#1) during the active high level KO1 period, as shown in FIG. 8 in which R.sub.0 denotes an on-impedance of (a pull-down transistor, not shown, of) the inverter driver 3(#1) in FIG. 6, V.sub.DD denotes power source positive voltage which is supplied to input signal lines m1 to m3 through pull-up resistors 5(#1) to 5(#3), resistance r represents that of key switch 1(#1) (refer to FIG. 3B), and resistance R.sub.1 corresponds to that of the pull-up resistor 5(#1) Further, an input impedance of inverter (receiver) 4(#1) is assumed to be sufficiently large.
With key switch 1(#1)=ON, and KO1="HIGH", an input voltage to the inverter (receiver) 4(#1) is obtained from FIG. 8 by VF(forward bias of the diode 2(#1), plus (VDD-VF) divided by a factor determined by resistances R.sub.1, r, R.sub.0 Namely, the receiver input voltage is given by ##EQU3## FIGS. 7E to 7G show inputs to the inverter (receiver) 4(#1), and FIGS. 7H to 7J show inputs to the terminal KI1 of the CPU7. Of these figures, FIGS. 7E and 7H represent a case 1 where a ratio of R.sub.0 +r to R.sub.1 which appears in equation (3) is correctly set, FIGS. 7F and 7I represent a case 2, when the pull-up resistance R.sub.1 is too large, and FIGS. 7G and 7J represent a case 3 when R.sub.1 is too small.
More specifically, with output KO1="HIGH",.both cases 1 and 2 see an input voltage to the inverter (receiver) 4(#1) smaller than the threshold voltage V.sub.TH as shown in FIGS. 7E and 7F so that a correct high level input voltage appears on the terminal KI1, indicative of an on-state of the key switch 1(#1), as shown in FIGS. 7H and 7I. On the contrary, in case 3 using a too small pull-up resistance, an input voltage to the inverter (driver) 4(#1) exceeds a threshold level V.sub.TH as shown in FIG. 7G, thus causing its output i.e., input voltage to the input terminal KI1 to assume a low level erroneously indicative of an off-state of the key switch 1(#1).
The worst status occurs when all key ,switches 1(#1), 1(#4) and 1(#7) are simultaneously actuated ON. FIG. 9 shows an equivalent circuit in the worst case with KO1="HIGH". Note that, impedances of inverters 4(#1) to 4(#3) are not shown because those are sufficiently large and their effect would be negligible. In this figure, R.sub.0 denotes an ON-resistance of the driver inverter 3(#1), r's represents resistances of on-state key switches 1(#1), 1(#4) and 1(#7), and three R.sub.1 's represent resistances of respective pull-up resistors 5(#1) to 5(#3).
In FIG. 9, a current flowing through driver resistance R.sub.0 is three times the current flowing through individual pull up resistance R.sub.1. Therefore, an input to the receiver inverter 4(#1) is given by ##EQU4## An influence of driver resistance R.sub.0 on the receiver input voltage level will become larger as the number of input signal lines increases. More specifically, if the number of input signal lines increases to n lines (i.e., m1 to m3), the influence increases in an order of n.times.R.sub.0. Therefore, it is desired to use inverters (drivers) 3(#1) to 3(#3) having a smaller value of on-impedance R.sub.0 with their input="HIGH" for reliable detection of simultaneous on-operations of a plural key switches.
However, as described in connection with arrangement the first prior art there is a lower limit to the value of the driver resistance R.sub.0 for manufacturing reasons. Whereas this problem could be solved by enlarging the value of the pull-up resistor R.sub.1 relative to the driver resistance R.sub.0 to attain a desired ratio of R.sub.0 to R.sub.1, this approach raises another problem similar to the one discussed above in connection with the first prior art arrangement.
In FIGS. 7A to 7J, such a problematic situation occurs during the high active output KO2 level period when CPU7
attempts to read the off-state key switch 1(#2) after having read the on-state key switch 1(#1) during the immediately preceding period of KO1="HIGH". Namely, an input level to the inverter (receiver) 4(#1) must go beyond the threshold level V.sub.TH (FIG. 7E) at the second READ pulse in FIG. 7D that occurs a predetermined time T from the rising edge of the pulse KO2, because the key switch 1(#2) is in an OFF status. Nevertheless, in case 2 using a relatively high pull-up resistance R.sub.1 , an input level to the inverter (receiver) (#1) is still smaller than V.sub.TH at the READ pulse time as shown in FIG. 7F, which causes its output i.e., input voltage to the terminal KI1, to assume a high level erroneously indicative of an on-state of the key switch 1(#2).
This is due to the capacitor 6(#1) (FIG. 6) having failed to sufficiently charge itself via R.sub.1 during a settling time T because the pull-up resistance R.sub.1 is too large.
The problem of misreading an off-state switch next to an on-state switch could be solved by lengthening a high level period on KO1 to KO3 as well as a waiting time T to a READ pulse in FIG. 7D. This obviously sacrifices a cycle time Ts required for a scanning of all the key switches. In summary, the first and second prior art arrangement can only use a key matrix circuit with a limited number of key switches to assure reliable key scanning within a limited time for detecting all key switches in the key matrix circuit.